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cc2430_sfr.h
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1 /**
2  *
3  * \file cc2430_sfr.h
4  * \brief CC2430 registers header file for CC2430.
5  *
6  * Definitions for CC2430 SFR registers.
7  *
8  *
9  */
10 
11 #ifndef REG_CC2430_H
12 #define REG_CC2430_H
13 
14 /* BYTE Register */
15 
16 __sfr __at (0x80) P0 ;
17 /* P0 */
18 __sbit __at (0x87) P0_7 ;
19 __sbit __at (0x86) P0_6 ;
20 __sbit __at (0x85) P0_5 ;
21 __sbit __at (0x84) P0_4 ;
22 __sbit __at (0x83) P0_3 ;
23 __sbit __at (0x82) P0_2 ;
24 __sbit __at (0x81) P0_1 ;
25 __sbit __at (0x80) P0_0 ;
26 
27 __sfr __at (0x81) SP ;
28 __sfr __at (0x82) DPL0 ;
29 __sfr __at (0x83) DPH0 ;
30 /*DPL and DPH correspond DPL0 and DPH0 (82-83)*/
31 __sfr __at (0x84) DPL1;
32 __sfr __at (0x85) DPH1;
33 __sfr __at (0x86) U0CSR;
34 #define U_MODE 0x80
35 #define U_RE 0x40
36 #define U_SLAVE 0x20
37 #define U_FE 0x10
38 #define U_ERR 0x08
39 #define U_RXB 0x04
40 #define U_TXB 0x02
41 #define U_ACTIVE 0x01
42 
43 __sfr __at (0x87) PCON ;
44 /* PCON (0x87) */
45 #define IDLE 0x01
46 
47 __sfr __at (0x88) TCON ;
48 /* TCON (0x88) */
49 __sbit __at (0x8F) TCON_URX1IF;
50 /*__sbit __at (0x8E) RES;*/
51 __sbit __at (0x8D) TCON_ADCIF;
52 /*__sbit __at (0x8C) RES;*/
53 __sbit __at (0x8B) TCON_URX0IF;
54 __sbit __at (0x8A) TCON_IT1;
55 __sbit __at (0x89) TCON_RFERRIF;
56 __sbit __at (0x88) TCON_IT0;
57 
58 
59 __sfr __at (0x89) P0IFG;
60 __sfr __at (0x8A) P1IFG;
61 __sfr __at (0x8B) P2IFG;
62 __sfr __at (0x8C) PICTL;
63 /*PICTL bits*/
64 #define PADSC 0x40
65 #define P2IEN 0x20
66 #define P0IENH 0x10
67 #define P0IENL 0x08
68 #define P2ICON 0x04
69 #define P1ICON 0x02
70 #define P0ICON 0x01
71 
72 __sfr __at (0x8D) P1IEN;
73 __sfr __at (0x8F) P0INP;
74 
75 __sfr __at (0x90) P1 ;
76 /* P1 */
77 __sbit __at (0x90) P1_0 ;
78 __sbit __at (0x91) P1_1 ;
79 __sbit __at (0x92) P1_2 ;
80 __sbit __at (0x93) P1_3 ;
81 __sbit __at (0x94) P1_4 ;
82 __sbit __at (0x95) P1_5 ;
83 __sbit __at (0x96) P1_6 ;
84 __sbit __at (0x97) P1_7 ;
85 
86 __sfr __at (0x91) RFIM;
87 __sfr __at (0x92) DPS;
88 __sfr __at (0x93) _XPAGE; /*MPAGE as paging register for sdcc*/
89 __sfr __at (0x94) T2CMP;
90 __sfr __at (0x95) ST0;
91 __sfr __at (0x96) ST1;
92 __sfr __at (0x97) ST2;
93 __sfr __at (0x98) S0CON ;
94 
95 __sbit __at (0x99) S0CON_ENCIF_1;
96 __sbit __at (0x98) S0CON_ENCIF_0;
97 
98 __sfr __at (0x99) HSRC;
99 __sfr __at (0x9A) IEN2;
100 /*IEN2 bits*/
101 #define WDTIE 0x20
102 #define P1IE 0x10
103 #define UTX1IE 0x08
104 #define UTX0IE 0x04
105 #define P2IE 0x02
106 #define RFIE 0x01
107 __sfr __at (0x9B) S1CON;
108 /*S1CON bits*/
109 #define RFIF_1 0x02
110 #define RFIF_0 0x01
111 __sfr __at (0x9C) T2PEROF0;
112 __sfr __at (0x9D) T2PEROF1;
113 __sfr __at (0x9E) T2PEROF2;
114 /*T2PEROF2 bits*/
115 #define CMPIM 0x80
116 #define PERIM 0x40
117 #define OFCMPIM 0x20
118 
119 #define PEROF23 0x08
120 #define PEROF22 0x04
121 #define PEROF21 0x02
122 #define PEROF20 0x01
123 
124 __sfr __at (0x9F) FMAP;
125 __sfr __at (0x9F) PSBANK;
126 
127 __sfr __at (0xA0) P2 ;
128 /* P2 */
129 __sbit __at (0xA0) P2_0 ;
130 __sbit __at (0xA1) P2_1 ;
131 __sbit __at (0xA2) P2_2 ;
132 __sbit __at (0xA3) P2_3 ;
133 __sbit __at (0xA4) P2_4 ;
134 /*__sbit __at (0xA5) P2_5 ;
135 __sbit __at (0xA6) P2_6 ;
136 __sbit __at (0xA7) P2_7 ;*/
137 
138 __sfr __at (0xA1) T2OF0;
139 __sfr __at (0xA2) T2OF1;
140 __sfr __at (0xA3) T2OF2;
141 __sfr __at (0xA4) T2CAPLPL;
142 __sfr __at (0xA5) T2CAPHPH;
143 __sfr __at (0xA6) T2TLD;
144 __sfr __at (0xA7) T2THD;
145 
146 __sfr __at (0xA8) IE ;
147 __sfr __at (0xA8) IEN0;
148 /*IEN0 bits*/
149 #define IEN0_EA_MASK 0x80
150 #define STIE 0x20
151 #define ENCIE 0x10
152 #define URX1IE 0x08
153 #define URX0IE 0x04
154 #define ADCIE 0x02
155 #define RFERRIE 0x01
156 /* IEN0 (0xA8) */
157 __sbit __at (0xAF) EA;
158 __sbit __at (0xAF) IEN0_EA;
159 /*__sbit __at (0xAE) RES;*/
160 __sbit __at (0xAD) IEN0_STIE;
161 __sbit __at (0xAC) IEN0_ENCIE;
162 __sbit __at (0xAB) IEN0_URX1IE;
163 __sbit __at (0xAA) IEN0_URX0IE;
164 __sbit __at (0xA9) IEN0_ADCIE;
165 __sbit __at (0xA8) IEN0_RFERRIE;
166 
167 __sfr __at (0xA9) IP0;
168 /*IP0 bits*/
169 #define IP0_5 0x20
170 #define IP0_4 0x10
171 #define IP0_3 0x08
172 #define IP0_2 0x04
173 #define IP0_1 0x02
174 #define IP0_0 0x01
175 __sfr __at (0xAB) FWT;
176 __sfr __at (0xAC) FADDRL;
177 __sfr __at (0xAD) FADDRH;
178 
179 __sfr __at (0xAE) FCTL;
180 #define F_BUSY 0x80
181 #define F_SWBSY 0x40
182 #define F_CONTRD 0x10
183 #define F_WRITE 0x02
184 #define F_ERASE 0x01
185 __sfr __at (0xAF) FWDATA;
186 
187 /*No port 3 (0xB0)*/
188 __sfr __at (0xB1) ENCDI;
189 __sfr __at (0xB2) ENCDO;
190 __sfr __at (0xB3) ENCCS;
191 #define CCS_MODE2 0x40
192 #define CCS_MODE1 0x20
193 #define CCS_MODE0 0x10
194 #define CCS_RDY 0x08
195 #define CCS_CMD1 0x04
196 #define CCS_CMD0 0x02
197 #define CCS_ST 0x01
198 __sfr __at (0xB4) ADCCON1;
199 /*ADCCON1 bits*/
200 #define ADEOC 0x80
201 #define ADST 0x40
202 #define ADSTS1 0x20
203 #define ADSTS0 0x10
204 #define ADRCTRL1 0x08
205 #define ADRCTRL0 0x04
206 __sfr __at (0xB5) ADCCON2;
207 /*ADCCON2 bits*/
208 #define ADSREF1 0x80
209 #define ADSREF0 0x40
210 #define ADSDIV1 0x20
211 #define ADSDIV0 0x10
212 #define ADSCH3 0x08
213 #define ADSCH2 0x04
214 #define ADSCH1 0x02
215 #define ADSCH0 0x01
216 __sfr __at (0xB6) ADCCON3;
217 /*ADCCON3 bits*/
218 #define ADEREF1 0x80
219 #define ADEREF0 0x40
220 #define ADEDIV1 0x20
221 #define ADEDIV0 0x10
222 #define ADECH3 0x08
223 #define ADECH2 0x04
224 #define ADECH1 0x02
225 #define ADECH0 0x01
226 
227 __sfr __at (0xB7) RCCTL;
228 #undef IP /*this is 0xb8 in base core*/
229 
230 __sfr __at (0xB8) IEN1;
231 /*IEN1 bits*/
232 #define P0IE 0x20
233 #define T4IE 0x10
234 #define T3IE 0x08
235 #define T2IE 0x04
236 #define T1IE 0x02
237 #define DMAIE 0x01
238 /* IEN1 (0xB8) */
239 /*__sbit __at (0xBF) IEN1_RES;*/
240 /*__sbit __at (0xBE) RES;*/
241 __sbit __at (0xBD) IEN1_P0IE;
242 __sbit __at (0xBC) IEN1_T4IE;
243 __sbit __at (0xBB) IEN1_T3IE;
244 __sbit __at (0xBA) IEN1_T2IE;
245 __sbit __at (0xB9) IEN1_T1IE;
246 __sbit __at (0xB8) IEN1_DMAIE;
247 
248 __sfr __at (0xB9) IP1;
249 /*IP1 bits*/
250 #define IP1_5 0x20
251 #define IP1_4 0x10
252 #define IP1_3 0x08
253 #define IP1_2 0x04
254 #define IP1_1 0x02
255 #define IP1_0 0x01
256 
257 __sfr __at (0xBA) ADCL;
258 __sfr __at (0xBB) ADCH;
259 __sfr __at (0xBC) RNDL;
260 __sfr __at (0xBD) RNDH;
261 
262 __sfr __at (0xBE) SLEEP;
263 #define XOSC_STB 0x40
264 #define HFRC_STB 0x20
265 #define RST1 0x10
266 #define RST0 0x08
267 #define OSC_PD 0x04
268 #define SLEEP_MODE1 0x02
269 #define SLEEP_MODE0 0x01
270 
271 __sfr __at (0xC0) IRCON;
272 /*IRCON bits*/
273 #define STIF 0x80
274 #define P0IF 0x20
275 #define T4IF 0x10
276 #define T3IF 0x08
277 #define T2IF 0x04
278 #define T1IF 0x02
279 #define DMAIF 0x01
280 /* IRCON */
281 __sbit __at (0xC7) IRCON_STIF ;
282 /*__sbit __at (0x86) IRCON_6 ;*/
283 __sbit __at (0xC5) IRCON_P0IF;
284 __sbit __at (0xC4) IRCON_T4IF;
285 __sbit __at (0xC3) IRCON_T3IF;
286 __sbit __at (0xC2) IRCON_T2IF;
287 __sbit __at (0xC1) IRCON_T1IF;
288 __sbit __at (0xC0) IRCON_DMAIF;
289 
290 __sfr __at (0xC1) U0BUF;
291 
292 __sfr __at (0xC2) U0BAUD;
293 __sfr __at (0xC3) T2CNF;
294 /*T2SEL bits*/
295 #define CMPIF 0x80
296 #define PERIF 0x40
297 #define OFCMPIF 0x20
298 
299 #define CMSEL 0x08
300 
301 #define SYNC 0x02
302 #define RUN 0x01
303 
304 __sfr __at (0xC4) U0UCR;
305 #define U_FLUSH 0x80
306 #define U_FLOW 0x40
307 #define U_D9 0x20
308 #define U_BIT9 0x10
309 #define U_PARITY 0x08
310 #define U_SPB 0x04
311 #define U_STOP 0x02
312 #define U_START 0x01
313 
314 __sfr __at (0xC5) U0GCR;
315 #define U_CPOL 0x80
316 #define U_CPHA 0x40
317 #define U_ORDER 0x20
318 #define U_BAUD_E4 0x10
319 #define U_BAUD_E3 0x08
320 #define U_BAUD_E2 0x04
321 #define U_BAUD_E1 0x02
322 #define U_BAUD_E0 0x01
323 
324 __sfr __at (0xC6) CLKCON;
325 #define OSC32K 0x80
326 #define OSC 0x40
327 #define TICKSPD2 0x20
328 #define TICKSPD1 0x10
329 #define TICKSPD0 0x08
330 #define CLKSPD 0x01
331 
332 __sfr __at (0xC7) MEMCTR;
333 #define MUNIF 0x40
334 __sfr __at (0xC8) T2CON;
335 
336 __sfr __at (0xC9) WDCTL;
337 #define WDT_CLR3 0x80
338 #define WDT_CLR2 0x40
339 #define WDT_CLR1 0x20
340 #define WDT_CLR0 0x10
341 #define WDT_EN 0x08
342 #define WDT_MODE 0x04
343 #define WDT_INT1 0x02
344 #define WDT_INT0 0x01
345 
346 __sfr __at (0xCA) T3CNT;
347 
348 __sfr __at (0xCB) T3CTL;
349 /*T3CTL bits*/
350 #define T3DIV2 0x80
351 #define T3DIV1 0x40
352 #define T3DIV0 0x20
353 #define T3START 0x10
354 #define T3OVFIM 0x08
355 #define T3CLR 0x04
356 #define T3MODE1 0x02
357 #define T3MODE0 0x01
358 
359 __sfr __at (0xCC) T3CCTL0;
360 /*T3CCTL0 bits*/
361 #define T3IM 0x40
362 #define T3CMP2 0x20
363 #define T3CMP1 0x10
364 #define T3CMP0 0x08
365 #define T3MODE 0x04
366 #define T3CAP1 0x02
367 #define T3CAP0 0x01
368 
369 __sfr __at (0xCD) T3CC0;
370 __sfr __at (0xCE) T3CCTL1;
371 /*T3CCTL0 bits apply*/
372 __sfr __at (0xCF) T3CC1;
373 
374 __sfr __at (0xD0) PSW ;
375 /* PSW */
376 __sbit __at (0xD0) P ;
377 __sbit __at (0xD1) F1 ;
378 __sbit __at (0xD2) OV ;
379 __sbit __at (0xD3) RS0 ;
380 __sbit __at (0xD4) RS1 ;
381 __sbit __at (0xD5) F0 ;
382 __sbit __at (0xD6) AC ;
383 __sbit __at (0xD7) CY ;
384 
385 __sfr __at (0xD1) DMAIRQ;
386 /*DMAIRQ bits*/
387 #define DMAIF4 0x10
388 #define DMAIF3 0x08
389 #define DMAIF2 0x04
390 #define DMAIF1 0x02
391 #define DMAIF0 0x01
392 
393 __sfr __at (0xD2) DMA1CFGL;
394 __sfr __at (0xD3) DMA1CFGH;
395 __sfr __at (0xD4) DMA0CFGL;
396 __sfr __at (0xD5) DMA0CFGH;
397 
398 __sfr __at (0xD6) DMAARM;
399 /*DMAARM bits*/
400 #define ABORT 0x80
401 #define DMAARM4 0x10
402 #define DMAARM3 0x08
403 #define DMAARM2 0x04
404 #define DMAARM1 0x02
405 #define DMAARM0 0x01
406 
407 __sfr __at (0xD7) DMAREQ;
408 /*DMAREQ bits*/
409 #define DMAREQ4 0x10
410 #define DMAREQ3 0x08
411 #define DMAREQ2 0x04
412 #define DMAREQ1 0x02
413 #define DMAREQ0 0x01
414 
415 __sfr __at (0xD8) TIMIF;
416 /*TIMIF bits*/
417 #define OVFIM 0x40
418 #define T4CH1IF 0x20
419 #define T4CH0IF 0x10
420 #define T4OVFIF 0x08
421 #define T3CH1IF 0x04
422 #define T3CH0IF 0x02
423 #define T3OVFIF 0x01
424 
425 __sfr __at (0xD9) RFD;
426 __sfr __at (0xDA) T1CC0L;
427 __sfr __at (0xDB) T1CC0H;
428 __sfr __at (0xDC) T1CC1L;
429 __sfr __at (0xDD) T1CC1H;
430 __sfr __at (0xDE) T1CC2L;
431 __sfr __at (0xDF) T1CC2H;
432 
433 __sfr __at (0xE0) ACC;
434 __sfr __at (0xE1) RFST;
435 __sfr __at (0xE2) T1CNTL;
436 __sfr __at (0xE3) T1CNTH;
437 
438 __sfr __at (0xE4) T1CTL;
439 /*T1CTL bits*/
440 #define CH2IF 0x80
441 #define CH1IF 0x40
442 #define CH0IF 0x20
443 #define OVFIF 0x10
444 #define T1DIV1 0x08
445 #define T1DIV0 0x04
446 #define T1MODE1 0x02
447 #define T1MODE0 0x01
448 
449 __sfr __at (0xE5) T1CCTL0;
450 /*T1CCTL0 bits*/
451 #define T1CPSEL 0x80
452 #define T1IM 0x40
453 #define T1CMP2 0x20
454 #define T1CMP1 0x10
455 #define T1CMP0 0x08
456 #define T1MODE 0x04
457 #define T1CAP1 0x02
458 #define T1CAP0 0x01
459 
460 __sfr __at (0xE6) T1CCTL1;
461 /*Bits defined in T1CCTL0 */
462 __sfr __at (0xE7) T1CCTL2;
463 /*Bits defined in T1CCTL0 */
464 __sfr __at (0xE8) IRCON2;
465 /*IRCON2 bits*/
466 #define WDTIF 0x10
467 #define P1IF 0x08
468 #define UTX1IF 0x04
469 #define UTX0IF 0x02
470 #define P2IF 0x01
471 /* IRCON 2 */
472 /*__sbit __at (0xEF) IRCON2_P1_7 ;
473 __sbit __at (0xEE) IRCON2_P1_6 ;
474 __sbit __at (0xED) IRCON2_P1_5 ;*/
475 __sbit __at (0xEC) IRCON2_WDTIF ;
476 __sbit __at (0xEB) IRCON2_P1IF ;
477 __sbit __at (0xEA) IRCON2_UTX1IF ;
478 __sbit __at (0xE9) IRCON2_UTX0IF ;
479 __sbit __at (0xE8) IRCON2_P2IF;
480 
481 
482 __sfr __at (0xE9) RFIF;
483 /*RFIF bits*/
484 #define IRQ_RREG_ON 0x80
485 #define IRQ_TXDONE 0x40
486 #define IRQ_FIFOP 0x20
487 #define IRQ_SFD 0x10
488 #define IRQ_CCA 0x08
489 #define IRQ_CSP_WT 0x04
490 #define IRQ_CSP_STOP 0x02
491 #define IRQ_CSP_INT 0x01
492 
493 __sfr __at (0xEA) T4CNT;
494 __sfr __at (0xEB) T4CTL;
495 /*T4CTL bits*/
496 #define T4DIV2 0x80
497 #define T4DIV1 0x40
498 #define T4DIV0 0x20
499 #define T4START 0x10
500 #define T4OVFIM 0x08
501 #define T4CLR 0x04
502 #define T4MODE1 0x02
503 #define T4MODE0 0x01
504 
505 __sfr __at (0xEC) T4CCTL0;
506 /*T4CCTL0 bits*/
507 #define T4IM 0x40
508 #define T4CMP2 0x20
509 #define T4CMP1 0x10
510 #define T4CMP0 0x08
511 #define T4MODE 0x04
512 #define T4CAP1 0x02
513 #define T4CAP0 0x01
514 
515 __sfr __at (0xED) T4CC0;
516 __sfr __at (0xEE) T4CCTL1;
517 /*T4CCTL0 bits apply*/
518 __sfr __at (0xEF) T4CC1;
519 
520 __sfr __at (0xF0) B ;
521 __sfr __at (0xF1) PERCFG;
522 /*PERCFG bits*/
523 #define T1CFG 0x40
524 #define T3CFG 0x20
525 #define T4CFG 0x10
526 #define U1CFG 0x02
527 #define U0CFG 0x01
528 
529 __sfr __at (0xF2) ADCCFG;
530 /*ADCCFG bits*/
531 #define ADC7EN 0x80
532 #define ADC6EN 0x40
533 #define ADC5EN 0x20
534 #define ADC4EN 0x10
535 #define ADC3EN 0x08
536 #define ADC2EN 0x04
537 #define ADC1EN 0x02
538 #define ADC0EN 0x01
539 
540 __sfr __at (0xF3) P0SEL;
541 __sfr __at (0xF4) P1SEL;
542 __sfr __at (0xF5) P2SEL;
543 /*P2SEL bits*/
544 #define PRI3P1 0x40
545 #define PRI2P1 0x20
546 #define PRI1P1 0x10
547 #define PRI0P1 0x08
548 #define SELP2_4 0x04
549 #define SELP2_3 0x02
550 #define SELP2_0 0x01
551 
552 __sfr __at (0xF6) P1INP;
553 
554 __sfr __at (0xF7) P2INP;
555 /*P2INP bits*/
556 #define PDUP2 0x80
557 #define PDUP1 0x40
558 #define PDUP0 0x20
559 #define MDP2_4 0x10
560 #define MDP2_3 0x08
561 #define MDP2_2 0x04
562 #define MDP2_1 0x02
563 #define MDP2_0 0x01
564 
565 __sfr __at (0xF8) U1CSR;
566 __sfr __at (0xF9) U1BUF;
567 __sfr __at (0xFA) U1BAUD;
568 __sfr __at (0xFB) U1UCR;
569 __sfr __at (0xFC) U1GCR;
570 __sfr __at (0xFD) P0DIR;
571 __sfr __at (0xFE) P1DIR;
572 
573 __sfr __at (0xFF) P2DIR;
574 /*P2DIR bits*/
575 #define PRI1P0 0x80
576 #define PRI0P0 0x40
577 #define DIRP2_4 0x10
578 #define DIRP2_3 0x08
579 #define DIRP2_2 0x04
580 #define DIRP2_1 0x02
581 #define DIRP2_0 0x01
582 
583 /* IEN0 */
584 /*__sbit __at (0xA8) EA ;
585 __sbit __at (0x99) TI ;
586 __sbit __at (0x9A) RB8 ;
587 __sbit __at (0x9B) TB8 ;
588 __sbit __at (0x9C) REN ;
589 __sbit __at (0x9D) SM2 ;
590 __sbit __at (0x9E) SM1 ;
591 __sbit __at (0x9F) SM0 ;*/
592 
593 
594 
595 /* Interrupt numbers: address = (number * 8) + 3 */
596 /*#undef IE0_VECTOR
597 #undef TF0_VECTOR
598 #undef IE1_VECTOR
599 #undef TF1_VECTOR
600 #undef SI0_VECTOR*/
601 
602 /* CC2430 interrupt vectors */
603 #define RFERR_VECTOR 0
604 #define ADC_VECTOR 1
605 #define URX0_VECTOR 2
606 #define URX1_VECTOR 3
607 #define ENC_VECTOR 4
608 #define ST_VECTOR 5
609 #define P2INT_VECTOR 6
610 #define UTX0_VECTOR 7
611 #define DMA_VECTOR 8
612 #define T1_VECTOR 9
613 #define T2_VECTOR 10
614 #define T3_VECTOR 11
615 #define T4_VECTOR 12
616 #define P0INT_VECTOR 13
617 #define UTX1_VECTOR 14
618 #define P1INT_VECTOR 15
619 #define RF_VECTOR 16
620 #define WDT_VECTOR 17
621 
622 /* RF control registers*/
623 __xdata __at (0xDF02) unsigned char MDMCTRL0H;
624 __xdata __at (0xDF03) unsigned char MDMCTRL0L;
625 __xdata __at (0xDF04) unsigned char MDMCTRL1H;
626 __xdata __at (0xDF05) unsigned char MDMCTRL1L;
627 __xdata __at (0xDF06) unsigned char RSSIH;
628 __xdata __at (0xDF07) unsigned char RSSIL;
629 __xdata __at (0xDF08) unsigned char SYNCWORDH;
630 __xdata __at (0xDF09) unsigned char SYNCWORDL;
631 __xdata __at (0xDF0A) unsigned char TXCTRLH;
632 __xdata __at (0xDF0B) unsigned char TXCTRLL;
633 __xdata __at (0xDF0C) unsigned char RXCTRL0H;
634 __xdata __at (0xDF0D) unsigned char RXCTRL0L;
635 __xdata __at (0xDF0E) unsigned char RXCTRL1H;
636 __xdata __at (0xDF0F) unsigned char RXCTRL1L;
637 __xdata __at (0xDF10) unsigned char FSCTRLH;
638 __xdata __at (0xDF11) unsigned char FSCTRLL;
639 __xdata __at (0xDF12) unsigned char CSPX;
640 __xdata __at (0xDF13) unsigned char CSPY;
641 __xdata __at (0xDF14) unsigned char CSPZ;
642 __xdata __at (0xDF15) unsigned char CSPCTRL;
643 __xdata __at (0xDF16) unsigned char CSPT;
644 __xdata __at (0xDF17) unsigned char RFPWR;
645 #define ADI_RADIO_PD 0x10
646 #define RREG_RADIO_PD 0x08
647 #define RREG_DELAY_MASK 0x07
648 
649 __xdata __at (0xDF20) unsigned char FSMTCH;
650 __xdata __at (0xDF21) unsigned char FSMTCL;
651 __xdata __at (0xDF22) unsigned char MANANDH;
652 __xdata __at (0xDF23) unsigned char MANANDL;
653 __xdata __at (0xDF24) unsigned char MANORH;
654 __xdata __at (0xDF25) unsigned char MANORL;
655 __xdata __at (0xDF26) unsigned char AGCCTRLH;
656 __xdata __at (0xDF27) unsigned char AGCCTRLL;
657 
658 __xdata __at (0xDF39) unsigned char FSMSTATE;
659 __xdata __at (0xDF3A) unsigned char ADCTSTH;
660 __xdata __at (0xDF3B) unsigned char ADCTSTL;
661 __xdata __at (0xDF3C) unsigned char DACTSTH;
662 __xdata __at (0xDF3D) unsigned char DACTSTL;
663 
664 __xdata __at (0xDF43) unsigned char IEEE_ADDR0;
665 __xdata __at (0xDF44) unsigned char IEEE_ADDR1;
666 __xdata __at (0xDF45) unsigned char IEEE_ADDR2;
667 __xdata __at (0xDF46) unsigned char IEEE_ADDR3;
668 __xdata __at (0xDF47) unsigned char IEEE_ADDR4;
669 __xdata __at (0xDF48) unsigned char IEEE_ADDR5;
670 __xdata __at (0xDF49) unsigned char IEEE_ADDR6;
671 __xdata __at (0xDF4A) unsigned char IEEE_ADDR7;
672 __xdata __at (0xDF4B) unsigned char PANIDH;
673 __xdata __at (0xDF4C) unsigned char PANIDL;
674 __xdata __at (0xDF4D) unsigned char SHORTADDRH;
675 __xdata __at (0xDF4E) unsigned char SHORTADDRL;
676 __xdata __at (0xDF4F) unsigned char IOCFG0;
677 __xdata __at (0xDF50) unsigned char IOCFG1;
678 __xdata __at (0xDF51) unsigned char IOCFG2;
679 __xdata __at (0xDF52) unsigned char IOCFG3;
680 __xdata __at (0xDF53) unsigned char RXFIFOCNT;
681 __xdata __at (0xDF54) unsigned char FSMTC1;
682 #define ABORTRX_ON_SRXON 0x20
683 #define RX_INTERRUPTED 0x10
684 #define AUTO_TX2RX_OFF 0x08
685 #define RX2RX_TIME_OFF 0x04
686 #define PENDING_OR 0x02
687 #define ACCEPT_ACKPKT 0x01
688 
689 __xdata __at (0xDF60) unsigned char CHVER;
690 __xdata __at (0xDF61) unsigned char CHIPID;
691 __xdata __at (0xDF62) unsigned char RFSTATUS;
692 #define TX_ACTIVE 0x10
693 #define FIFO 0x08
694 #define FIFOP 0x04
695 #define SFD 0x02
696 #define CCA 0x01
697 
698 __xdata __at (0xDFC1) unsigned char U0BUF_SHADOW;
699 
700 __xdata __at (0xDFD9) unsigned char RFD_SHADOW;
701 
702 __xdata __at (0xDFF9) unsigned char U1BUF_SHADOW;
703 
704 __xdata __at (0xDFBA) unsigned int ADC_SHADOW;
705 
706 #endif /*REG_CC2430*/
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