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stm32f10x_nvic.h
1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
2 * File Name : stm32f10x_nvic.h
3 * Author : MCD Application Team
4 * Version : V2.0.3
5 * Date : 09/22/2008
6 * Description : This file contains all the functions prototypes for the
7 * NVIC firmware library.
8 ********************************************************************************
9 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
10 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
11 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
12 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
13 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
14 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
15 *******************************************************************************/
16 
17 /* Define to prevent recursive inclusion -------------------------------------*/
18 #ifndef __STM32F10x_NVIC_H
19 #define __STM32F10x_NVIC_H
20 
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_map.h"
23 
24 /* Exported types ------------------------------------------------------------*/
25 /* NVIC Init Structure definition */
26 typedef struct
27 {
28  u8 NVIC_IRQChannel;
29  u8 NVIC_IRQChannelPreemptionPriority;
30  u8 NVIC_IRQChannelSubPriority;
31  FunctionalState NVIC_IRQChannelCmd;
32 } NVIC_InitTypeDef;
33 
34 /* Exported constants --------------------------------------------------------*/
35 /* IRQ Channels --------------------------------------------------------------*/
36 #define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */
37 #define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */
38 #define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */
39 #define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */
40 #define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */
41 #define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */
42 #define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */
43 #define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */
44 #define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */
45 #define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */
46 #define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */
47 #define DMA1_Channel1_IRQChannel ((u8)0x0B) /* DMA1 Channel 1 global Interrupt */
48 #define DMA1_Channel2_IRQChannel ((u8)0x0C) /* DMA1 Channel 2 global Interrupt */
49 #define DMA1_Channel3_IRQChannel ((u8)0x0D) /* DMA1 Channel 3 global Interrupt */
50 #define DMA1_Channel4_IRQChannel ((u8)0x0E) /* DMA1 Channel 4 global Interrupt */
51 #define DMA1_Channel5_IRQChannel ((u8)0x0F) /* DMA1 Channel 5 global Interrupt */
52 #define DMA1_Channel6_IRQChannel ((u8)0x10) /* DMA1 Channel 6 global Interrupt */
53 #define DMA1_Channel7_IRQChannel ((u8)0x11) /* DMA1 Channel 7 global Interrupt */
54 #define ADC1_2_IRQChannel ((u8)0x12) /* ADC1 et ADC2 global Interrupt */
55 #define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */
56 #define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */
57 #define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */
58 #define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */
59 #define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */
60 #define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */
61 #define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */
62 #define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */
63 #define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */
64 #define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */
65 #define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */
66 #define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */
67 #define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */
68 #define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */
69 #define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */
70 #define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */
71 #define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */
72 #define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */
73 #define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */
74 #define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */
75 #define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */
76 #define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */
77 #define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */
78 #define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */
79 #define TIM8_BRK_IRQChannel ((u8)0x2B) /* TIM8 Break Interrupt */
80 #define TIM8_UP_IRQChannel ((u8)0x2C) /* TIM8 Update Interrupt */
81 #define TIM8_TRG_COM_IRQChannel ((u8)0x2D) /* TIM8 Trigger and Commutation Interrupt */
82 #define TIM8_CC_IRQChannel ((u8)0x2E) /* TIM8 Capture Compare Interrupt */
83 #define ADC3_IRQChannel ((u8)0x2F) /* ADC3 global Interrupt */
84 #define FSMC_IRQChannel ((u8)0x30) /* FSMC global Interrupt */
85 #define SDIO_IRQChannel ((u8)0x31) /* SDIO global Interrupt */
86 #define TIM5_IRQChannel ((u8)0x32) /* TIM5 global Interrupt */
87 #define SPI3_IRQChannel ((u8)0x33) /* SPI3 global Interrupt */
88 #define UART4_IRQChannel ((u8)0x34) /* UART4 global Interrupt */
89 #define UART5_IRQChannel ((u8)0x35) /* UART5 global Interrupt */
90 #define TIM6_IRQChannel ((u8)0x36) /* TIM6 global Interrupt */
91 #define TIM7_IRQChannel ((u8)0x37) /* TIM7 global Interrupt */
92 #define DMA2_Channel1_IRQChannel ((u8)0x38) /* DMA2 Channel 1 global Interrupt */
93 #define DMA2_Channel2_IRQChannel ((u8)0x39) /* DMA2 Channel 2 global Interrupt */
94 #define DMA2_Channel3_IRQChannel ((u8)0x3A) /* DMA2 Channel 3 global Interrupt */
95 #define DMA2_Channel4_5_IRQChannel ((u8)0x3B) /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */
96 
97 
98 #define IS_NVIC_IRQ_CHANNEL(CHANNEL) (((CHANNEL) == WWDG_IRQChannel) || \
99  ((CHANNEL) == PVD_IRQChannel) || \
100  ((CHANNEL) == TAMPER_IRQChannel) || \
101  ((CHANNEL) == RTC_IRQChannel) || \
102  ((CHANNEL) == FLASH_IRQChannel) || \
103  ((CHANNEL) == RCC_IRQChannel) || \
104  ((CHANNEL) == EXTI0_IRQChannel) || \
105  ((CHANNEL) == EXTI1_IRQChannel) || \
106  ((CHANNEL) == EXTI2_IRQChannel) || \
107  ((CHANNEL) == EXTI3_IRQChannel) || \
108  ((CHANNEL) == EXTI4_IRQChannel) || \
109  ((CHANNEL) == DMA1_Channel1_IRQChannel) || \
110  ((CHANNEL) == DMA1_Channel2_IRQChannel) || \
111  ((CHANNEL) == DMA1_Channel3_IRQChannel) || \
112  ((CHANNEL) == DMA1_Channel4_IRQChannel) || \
113  ((CHANNEL) == DMA1_Channel5_IRQChannel) || \
114  ((CHANNEL) == DMA1_Channel6_IRQChannel) || \
115  ((CHANNEL) == DMA1_Channel7_IRQChannel) || \
116  ((CHANNEL) == ADC1_2_IRQChannel) || \
117  ((CHANNEL) == USB_HP_CAN_TX_IRQChannel) || \
118  ((CHANNEL) == USB_LP_CAN_RX0_IRQChannel) || \
119  ((CHANNEL) == CAN_RX1_IRQChannel) || \
120  ((CHANNEL) == CAN_SCE_IRQChannel) || \
121  ((CHANNEL) == EXTI9_5_IRQChannel) || \
122  ((CHANNEL) == TIM1_BRK_IRQChannel) || \
123  ((CHANNEL) == TIM1_UP_IRQChannel) || \
124  ((CHANNEL) == TIM1_TRG_COM_IRQChannel) || \
125  ((CHANNEL) == TIM1_CC_IRQChannel) || \
126  ((CHANNEL) == TIM2_IRQChannel) || \
127  ((CHANNEL) == TIM3_IRQChannel) || \
128  ((CHANNEL) == TIM4_IRQChannel) || \
129  ((CHANNEL) == I2C1_EV_IRQChannel) || \
130  ((CHANNEL) == I2C1_ER_IRQChannel) || \
131  ((CHANNEL) == I2C2_EV_IRQChannel) || \
132  ((CHANNEL) == I2C2_ER_IRQChannel) || \
133  ((CHANNEL) == SPI1_IRQChannel) || \
134  ((CHANNEL) == SPI2_IRQChannel) || \
135  ((CHANNEL) == USART1_IRQChannel) || \
136  ((CHANNEL) == USART2_IRQChannel) || \
137  ((CHANNEL) == USART3_IRQChannel) || \
138  ((CHANNEL) == EXTI15_10_IRQChannel) || \
139  ((CHANNEL) == RTCAlarm_IRQChannel) || \
140  ((CHANNEL) == USBWakeUp_IRQChannel) || \
141  ((CHANNEL) == TIM8_BRK_IRQChannel) || \
142  ((CHANNEL) == TIM8_UP_IRQChannel) || \
143  ((CHANNEL) == TIM8_TRG_COM_IRQChannel) || \
144  ((CHANNEL) == TIM8_CC_IRQChannel) || \
145  ((CHANNEL) == ADC3_IRQChannel) || \
146  ((CHANNEL) == FSMC_IRQChannel) || \
147  ((CHANNEL) == SDIO_IRQChannel) || \
148  ((CHANNEL) == TIM5_IRQChannel) || \
149  ((CHANNEL) == SPI3_IRQChannel) || \
150  ((CHANNEL) == UART4_IRQChannel) || \
151  ((CHANNEL) == UART5_IRQChannel) || \
152  ((CHANNEL) == TIM6_IRQChannel) || \
153  ((CHANNEL) == TIM7_IRQChannel) || \
154  ((CHANNEL) == DMA2_Channel1_IRQChannel) || \
155  ((CHANNEL) == DMA2_Channel2_IRQChannel) || \
156  ((CHANNEL) == DMA2_Channel3_IRQChannel) || \
157  ((CHANNEL) == DMA2_Channel4_5_IRQChannel))
158 
159 
160 /* System Handlers -----------------------------------------------------------*/
161 #define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */
162 #define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */
163 #define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */
164 #define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */
165 #define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */
166 #define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */
167 #define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */
168 #define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */
169 #define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */
170 
171 #define IS_CONFIG_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
172  ((HANDLER) == SystemHandler_BusFault) || \
173  ((HANDLER) == SystemHandler_UsageFault))
174 
175 #define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
176  ((HANDLER) == SystemHandler_BusFault) || \
177  ((HANDLER) == SystemHandler_UsageFault) || \
178  ((HANDLER) == SystemHandler_SVCall) || \
179  ((HANDLER) == SystemHandler_DebugMonitor) || \
180  ((HANDLER) == SystemHandler_PSV) || \
181  ((HANDLER) == SystemHandler_SysTick))
182 
183 #define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
184  ((HANDLER) == SystemHandler_BusFault) || \
185  ((HANDLER) == SystemHandler_SVCall))
186 
187 #define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_NMI) || \
188  ((HANDLER) == SystemHandler_PSV) || \
189  ((HANDLER) == SystemHandler_SysTick))
190 
191 #define IS_CLEAR_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_PSV) || \
192  ((HANDLER) == SystemHandler_SysTick))
193 
194 #define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
195  ((HANDLER) == SystemHandler_BusFault) || \
196  ((HANDLER) == SystemHandler_UsageFault) || \
197  ((HANDLER) == SystemHandler_SVCall) || \
198  ((HANDLER) == SystemHandler_DebugMonitor) || \
199  ((HANDLER) == SystemHandler_PSV) || \
200  ((HANDLER) == SystemHandler_SysTick))
201 
202 #define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_HardFault) || \
203  ((HANDLER) == SystemHandler_MemoryManage) || \
204  ((HANDLER) == SystemHandler_BusFault) || \
205  ((HANDLER) == SystemHandler_UsageFault) || \
206  ((HANDLER) == SystemHandler_DebugMonitor))
207 
208 #define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
209  ((HANDLER) == SystemHandler_BusFault))
210 
211 
212 /* Vector Table Base ---------------------------------------------------------*/
213 #define NVIC_VectTab_RAM ((u32)0x20000000)
214 #define NVIC_VectTab_FLASH ((u32)0x08000000)
215 
216 #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
217  ((VECTTAB) == NVIC_VectTab_FLASH))
218 
219 /* System Low Power ----------------------------------------------------------*/
220 #define NVIC_LP_SEVONPEND ((u8)0x10)
221 #define NVIC_LP_SLEEPDEEP ((u8)0x04)
222 #define NVIC_LP_SLEEPONEXIT ((u8)0x02)
223 
224 #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
225  ((LP) == NVIC_LP_SLEEPDEEP) || \
226  ((LP) == NVIC_LP_SLEEPONEXIT))
227 
228 /* Preemption Priority Group -------------------------------------------------*/
229 #define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority
230  4 bits for subpriority */
231 #define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority
232  3 bits for subpriority */
233 #define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority
234  2 bits for subpriority */
235 #define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority
236  1 bits for subpriority */
237 #define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority
238  0 bits for subpriority */
239 
240 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
241  ((GROUP) == NVIC_PriorityGroup_1) || \
242  ((GROUP) == NVIC_PriorityGroup_2) || \
243  ((GROUP) == NVIC_PriorityGroup_3) || \
244  ((GROUP) == NVIC_PriorityGroup_4))
245 
246 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
247 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
248 #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
249 #define IS_NVIC_BASE_PRI(PRI) ((PRI) < 0x10)
250 
251 /* Exported macro ------------------------------------------------------------*/
252 /* Exported functions ------------------------------------------------------- */
253 void NVIC_DeInit(void);
254 void NVIC_SCBDeInit(void);
255 void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);
256 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
257 void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);
258 void NVIC_SETPRIMASK(void);
259 void NVIC_RESETPRIMASK(void);
260 void NVIC_SETFAULTMASK(void);
261 void NVIC_RESETFAULTMASK(void);
262 void NVIC_BASEPRICONFIG(u32 NewPriority);
263 u32 NVIC_GetBASEPRI(void);
264 u16 NVIC_GetCurrentPendingIRQChannel(void);
265 ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);
266 void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);
267 void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);
268 u16 NVIC_GetCurrentActiveHandler(void);
269 ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);
270 u32 NVIC_GetCPUID(void);
271 void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);
272 void NVIC_GenerateSystemReset(void);
273 void NVIC_GenerateCoreReset(void);
274 void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);
275 void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);
276 void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
277  u8 SystemHandlerSubPriority);
278 ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);
279 void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);
280 void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);
281 ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);
282 u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);
283 u32 NVIC_GetFaultAddress(u32 SystemHandler);
284 
285 #endif /* __STM32F10x_NVIC_H */
286 
287 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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