Contiki 2.5
rtimer-arch.c
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1 /*
2  * Copyright (c) 2007, Swedish Institute of Computer Science.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
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9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
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13  * 3. Neither the name of the Institute nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * This file is part of the Contiki operating system.
30  *
31  * $Id: rtimer-arch.c,v 1.10 2010/02/28 21:29:19 dak664 Exp $
32  */
33 
34 /**
35  * \file
36  * AVR-specific rtimer code
37  * Defaults to Timer3 for those ATMEGAs that have it.
38  * If Timer3 not present Timer1 will be used.
39  * \author
40  * Fredrik Osterlind <fros@sics.se>
41  * Joakim Eriksson <joakime@sics.se>
42  */
43 
44 /* OBS: 8 seconds maximum time! */
45 
46 #include <avr/io.h>
47 #include <avr/interrupt.h>
48 #include <stdio.h>
49 
50 #include "sys/energest.h"
51 #include "sys/rtimer.h"
52 #include "rtimer-arch.h"
53 
54 #if defined(__AVR_ATmega1281__) || defined(__AVR_ATmega1284P__)
55 #define ETIMSK TIMSK3
56 #define ETIFR TIFR3
57 #define TICIE3 ICIE3
58 
59 //Has no 'C', so we just set it to B. The code doesn't really use C so this
60 //is safe to do but lets it compile. Probably should enable the warning if
61 //it is ever used on other platforms.
62 //#warning no OCIE3C in timer3 architecture, hopefully it won't be needed!
63 
64 #define OCIE3C OCIE3B
65 #define OCF3C OCF3B
66 #endif
67 
68 #if defined(__AVR_AT90USB1287__) || defined(__AVR_ATmega128RFA1__)
69 #define ETIMSK TIMSK3
70 #define ETIFR TIFR3
71 #define TICIE3 ICIE3
72 #endif
73 
74 #if defined(__AVR_ATmega328P__) || defined(__AVR_ATmega644__)
75 #define TIMSK TIMSK1
76 #define TICIE1 ICIE1
77 #define TIFR TIFR1
78 #endif
79 
80 /* Track flow through rtimer interrupts*/
81 #if DEBUGFLOWSIZE&&0
82 extern uint8_t debugflowsize,debugflow[DEBUGFLOWSIZE];
83 #define DEBUGFLOW(c) if (debugflowsize<(DEBUGFLOWSIZE-1)) debugflow[debugflowsize++]=c
84 #else
85 #define DEBUGFLOW(c)
86 #endif
87 
88 /*---------------------------------------------------------------------------*/
89 #if defined(TCNT3) && RTIMER_ARCH_PRESCALER
90 ISR (TIMER3_COMPA_vect) {
91  DEBUGFLOW('/');
92  ENERGEST_ON(ENERGEST_TYPE_IRQ);
93 
94  /* Disable rtimer interrupts */
95  ETIMSK &= ~((1 << OCIE3A) | (1 << OCIE3B) | (1 << TOIE3) |
96  (1 << TICIE3) | (1 << OCIE3C));
97 
98 #if RTIMER_CONF_NESTED_INTERRUPTS
99  /* Enable nested interrupts. Allows radio interrupt during rtimer interrupt. */
100  /* All interrupts are enabled including recursive rtimer, so use with caution */
101  sei();
102 #endif
103 
104  /* Call rtimer callback */
105  rtimer_run_next();
106 
107  ENERGEST_OFF(ENERGEST_TYPE_IRQ);
108  DEBUGFLOW('\\');
109 }
110 
111 #elif RTIMER_ARCH_PRESCALER
112 #warning "No Timer3 in rtimer-arch.c - using Timer1 instead"
113 ISR (TIMER1_COMPA_vect) {
114  DEBUGFLOW('/');
115  TIMSK &= ~((1<<TICIE1)|(1<<OCIE1A)|(1<<OCIE1B)|(1<<TOIE1));
116 
117  rtimer_run_next();
118  DEBUGFLOW('\\');
119 }
120 
121 #endif
122 /*---------------------------------------------------------------------------*/
123 void
124 rtimer_arch_init(void)
125 {
126 #if RTIMER_ARCH_PRESCALER
127  /* Disable interrupts (store old state) */
128  uint8_t sreg;
129  sreg = SREG;
130  cli ();
131 
132 #ifdef TCNT3
133  /* Disable all timer functions */
134  ETIMSK &= ~((1 << OCIE3A) | (1 << OCIE3B) | (1 << TOIE3) |
135  (1 << TICIE3) | (1 << OCIE3C));
136  /* Write 1s to clear existing timer function flags */
137  ETIFR |= (1 << ICF3) | (1 << OCF3A) | (1 << OCF3B) | (1 << TOV3) |
138  (1 << OCF3C);
139 
140  /* Default timer behaviour */
141  TCCR3A = 0;
142  TCCR3B = 0;
143  TCCR3C = 0;
144 
145  /* Reset counter */
146  TCNT3 = 0;
147 
148 #if RTIMER_ARCH_PRESCALER==1024
149  TCCR3B |= 5;
150 #elif RTIMER_ARCH_PRESCALER==256
151  TCCR3B |= 4;
152 #elif RTIMER_ARCH_PRESCALER==64
153  TCCR3B |= 3;
154 #elif RTIMER_ARCH_PRESCALER==8
155  TCCR3B |= 2;
156 #elif RTIMER_ARCH_PRESCALER==1
157  TCCR3B |= 1;
158 #else
159 #error Timer3 PRESCALER factor not supported.
160 #endif
161 
162 #elif RTIMER_ARCH_PRESCALER
163  /* Leave timer1 alone if PRESCALER set to zero */
164  /* Obviously you can not then use rtimers */
165 
166  TIMSK &= ~((1<<TICIE1)|(1<<OCIE1A)|(1<<OCIE1B)|(1<<TOIE1));
167  TIFR |= (1 << ICF1) | (1 << OCF1A) | (1 << OCF1B) | (1 << TOV1);
168 
169  /* Default timer behaviour */
170  TCCR1A = 0;
171  TCCR1B = 0;
172 
173  /* Reset counter */
174  TCNT1 = 0;
175 
176  /* Start clock */
177 #if RTIMER_ARCH_PRESCALER==1024
178  TCCR1B |= 5;
179 #elif RTIMER_ARCH_PRESCALER==256
180  TCCR1B |= 4;
181 #elif RTIMER_ARCH_PRESCALER==64
182  TCCR1B |= 3;
183 #elif RTIMER_ARCH_PRESCALER==8
184  TCCR1B |= 2;
185 #elif RTIMER_ARCH_PRESCALER==1
186  TCCR1B |= 1;
187 #else
188 #error Timer1 PRESCALER factor not supported.
189 #endif
190 
191 #endif /* TCNT3 */
192 
193  /* Restore interrupt state */
194  SREG = sreg;
195 #endif /* RTIMER_ARCH_PRESCALER */
196 }
197 /*---------------------------------------------------------------------------*/
198 void
199 rtimer_arch_schedule(rtimer_clock_t t)
200 {
201 #if RTIMER_ARCH_PRESCALER
202  /* Disable interrupts (store old state) */
203  uint8_t sreg;
204  sreg = SREG;
205  cli ();
206  DEBUGFLOW(':');
207 #ifdef TCNT3
208  /* Set compare register */
209  OCR3A = t;
210  /* Write 1s to clear all timer function flags */
211  ETIFR |= (1 << ICF3) | (1 << OCF3A) | (1 << OCF3B) | (1 << TOV3) |
212  (1 << OCF3C);
213  /* Enable interrupt on OCR3A match */
214  ETIMSK |= (1 << OCIE3A);
215 
216 #elif RTIMER_ARCH_PRESCALER
217  /* Set compare register */
218  OCR1A = t;
219  TIFR |= (1 << ICF1) | (1 << OCF1A) | (1 << OCF1B) | (1 << TOV1);
220  TIMSK |= (1 << OCIE1A);
221 
222 #endif
223 
224  /* Restore interrupt state */
225  SREG = sreg;
226 #endif /* RTIMER_ARCH_PRESCALER */
227 }